1. Field of the Invention
This invention relates to a process for manufacturing a semiconductor wafer and also to a process for using and utilizing such a semiconductor wafer.
More particularly, the present invention relates to a process for manufacturing a semiconductor wafer that can be used for producing a semiconductor device such as a microprocessor, a memory, a logic circuit, a system LSI, a solar battery, an image sensor, a light emitting device or a display device, as a monitor wafer such as a film thickness monitor to be used for forming a film, an etching depth monitor to be used for an etching operation or a particle monitor to be used for detecting and counting foreign particles or as a dummy wafer to be used in a processing system in order to regulate various processing conditions for film formation, heat treatment, doping or etching. It also relates to a method of using and utilizing such a semiconductor wafer. Specifically, the present invention is adapted to manufacture semiconductor wafers of different types that can be used and utilized in different applications.
2. Related Background Art
Semiconductor wafers having layers of various semiconductor materials such as Si, GaAs, InP and GaN are known. Particularly, SOI wafers comprising a support substrate having an insulating surface and a semiconductor layer formed thereon are attracting attention as they are highly adapted to preparing semiconductor devices that operate at high speed with a low power consumption. For the purpose of this invention, an SOI wafer refers to a wafer carrying a semiconductor on an insulator, which may not necessarily be a wafer carrying silicon on an insulator.
Known SOI wafers include SIMOX wafers prepared through oxygen ion implantation and heat treatment and bonded wafers such as those described in Japanese Patent Application Laid-Open No. 5-211128, U.S. Pat. No. 5,374,564 and Japanese Patent Application Laid-Open No. 10-200080 and prepared through hydrogen ion implantation and peeling as well as the one described in International Patent Publication W098/52216 and prepared through plasma immersion ion implantation (PIII). Japanese Patent Application Laid-Open No. 2608351 and U.S. Pat. No. 5,371,037 describe respective methods of preparing a high quality SOI wafer by transferring an epitaxial layer on a separate support substrate.
Japanese Patent Application Laid-Open No. 7-302889 (U.S. Pat. No. 5,856,229) proposes an improved method for transferring an epitaxial layer.
FIGS. 17A through 17E schematically illustrate the known method for transferring an epitaxial layer.
Firstly, as shown in FIG. 17A, a semiconductor wafer that is an Si wafer (which may be referred to as prime wafer, bond wafer, device wafer or seed wafer) is brought in and the surface anodized to produce a porous layer 4 on the surface.
Then, as shown in FIG. 17B, a non-porous monocrystalline semiconductor layer 5 is formed on the porous layer 4 by epitaxial growth, typically using a CVD technique.
Thereafter, as shown in FIG. 17C, the surface of the epitaxial layer (non-porous monocrystalline semiconductor layer) is oxidized to produce an insulating layer 6. Then, said insulating layer 6 is brought to contact with and bonded to the surface of another semiconductor wafer 2 (or a piece of quartz glass). Thus, a multilayer structure containing the epitaxial layer 5 in the inside is prepared.
Then, as shown in FIG. 17D, the multilayer structure is subjected to external force or internal stress typically by inserting a wedge into a lateral side thereof or heating the multilayer structure in order to split it along the porous layer (reference numerals 41 and 42 in FIG. 17D shows the split porous layer).
Then, the porous layer 4B remaining on the surface of the epitaxial layer 5 that has been transferred to the second semiconductor wafer 2 (also referred to as handle wafer or base wafer) is removed by wet etching, using a mixture solution of hydrofluoric acid and hydrogen peroxide. Then, as shown in FIG. 17E, the exposed epitaxial layer is smoothed typically by hydrogen annealing to produce a finished SOI that has remarkable characteristics.
On the other hand, the separated Si wafer still maintains the profile of a thin disk. Therefore, it can be used as Si wafer 1 for preparing another SOI wafer as shown in FIG. 17A for another time after removing the porous layer remaining on the cleaved side thereof also by wet etching, using the same solution. Alternatively, it may be used as semiconductor wafer 2 for preparing another SOI wafer as shown in FIG. 17B.
As described above, Japanese Patent Application Laid-Open No. 7-302889 discloses a method of reusing a peeled Si wafer as Si wafer 1 as shown in FIG. 17A or as semiconductor wafer 2 as shown in FIG. 17B.
However, the above described method is accompanied by several problems to be dissolved.
For instance, when an Si wafer is repeatedly reused as the first wafer, it gradually loses its thickness because its surface layer is turned into a porous layer for another time and the produced porous layer is subsequently removed. Therefore, each reuse of such an Si wafer may require a cumbersome process of adjusting the conditions under which it is reused by forming a porous layer on the surface to consequently reduce its thickness further. Additionally, if a multilayer structure is produced, it can be sensitively affected by the thickness of the first wafer and those of other layers to become swerved under certain conditions. Thus, it is highly important to rigorously control the thickness of the first wafer.
Additionally, the damage to the Si wafer that occurred in the separating step may adversely affect the subsequent steps including that of producing a porous layer to make it no longer usable for manufacturing SOI wafers having the same and identical characteristics.
Still additionally, the process of manufacturing SOI wafers is far more complex than that of manufacturing bulk wafers and hence the yield of manufacturing SOI wafers is normally rather low. In other words, if the reusable first wafer is actually reused as the first or second wafer for preparing another SOI wafer, it may not satisfactorily be used on a commercial basis from the viewpoint of attaining a necessary quality level.
While the above known method of reusing an Si wafer is intended to reuse the first wafer that is recovered after the process of manufacturing an SOI wafer for manufacturing another SOI wafer of the same quality, the Si wafer is normally short of meeting the requirements of a commercially feasible wafer of the type under consideration.
Then, such an Si wafer may have no value from the viewpoint of reducing waste and exploiting limited resources in the industry of the near future.
An object of the present invention is to provide a process for manufacturing a semiconductor wafer which has superior suitability for mass production and reproducibility.
It is another object of the present invention to provide a process for manufacturing a semiconductor wafer which improves economic efficiency and provides SOI wafers having excellent quality without decreasing the number of wafers on the market.
A process for manufacturing a semiconductor wafer according to the present invention comprises the steps of:
preparing a first member which has a semiconductor layer on a semiconductor substrate;
transferring said semiconductor layer onto a second member after separating said semiconductor layer from said first member; and
smoothing the surface of said semiconductor substrate after said transferring step so as to use said semiconductor substrate as a semiconductor wafer for purposes other than forming said first and second members.
Moreover, a process for manufacturing a semiconductor wafer according to the present invention comprises the steps of:
preparing a first member which has a semiconductor layer on a semiconductor substrate with a separation layer arranged therebetween;
transferring said semiconductor layer onto a second member after separating said semiconductor layer through said separation layer; and
smoothing the surface of said semiconductor substrate after said transferring step so as to use said semiconductor substrate as a semiconductor wafer for purposes other than forming said first and second members.
A process for manufacturing a semiconductor wafer according to the present invention comprises the steps of:
preparing a first member which has a semiconductor layer on a p-type semiconductor substrate;
separating said semiconductor layer from said first member to transfer the semiconductor layer onto a second member, thereby forming a first semiconductor wafer; and
conducting epitaxial growth of a low concentration p-type semiconductor layer on said p-type semiconductor substrate from which said semiconductor layer has been separated, said low concentration p-type semiconductor layer having an impurity concentration, which defines p-type conductivity, lower than that of said p-type semiconductor substrate.
A process for manufacturing a semiconductor wafer according to the present invention comprises the steps of:
preparing a first member which has a semiconductor layer on a p-type semiconductor substrate with a separation layer arranged therebetween;
separating said semiconductor layer through said separation layer to transfer the semiconductor layer onto a second member, thereby forming a first semiconductor wafer; and
conducting epitaxial growth of a low concentration p-type semiconductor layer on said p-type semiconductor substrate which has been separated through said separation layer, said low concentration p-type semiconductor layer having impurity concentration, which defines p-type conductivity, lower than that of said p-type semiconductor substrate.
A process for manufacturing a semiconductor wafer according to the present invention comprises the steps of:
forming a separation layer within a p-type semiconductor substrate to form a first member which has a semiconductor layer on said separation layer;
separating said semiconductor layer through said separation layer to transfer the semiconductor layer onto a second member, thereby forming a first semiconductor wafer; and
conducting epitaxial growth of a low concentration p-type semiconductor layer on said p-type semiconductor substrate which has been separated through said separation layer, said low concentration p-type semiconductor layer having impurity concentration, which defines p-type conductivity, lower than that of said p-type semiconductor substrate.
A process for manufacturing a semiconductor wafer according to the present invention comprises steps of:
preparing a first member which has a semiconductor layer on a p-type semiconductor substrate with a separation layer arranged therebetween;
bonding said first member with a second member to form a multilayer structure;
conducting heat-treatment of said multilayer structure under an oxidizing atmosphere
separating said multilayer structure through said separation layer to transfer said semiconductor layer onto a second member, thereby forming a first semiconductor wafer; and
conducting epitaxial growth of a low concentration p-type semiconductor layer on said p-type semiconductor substrate which has been separated through said separation layer, said low concentration p-type semiconductor layer having impurity concentration, which defines p-type conductivity, lower than that of said p-type semiconductor substrate.
A process for manufacturing a semiconductor wafer according to the present invention comprises the steps of:
preparing a first member which has at least a first semiconductor layer comprising an epitaxial semiconductor layer having impurity concentration, which defines p-type conductivity, lower than that of a p-type semiconductor substrate, a separation layer, and a second semiconductor layer, arranged on said p-type semiconductor substrate in that order; and
forming a first semiconductor wafer by transferring said second semiconductor layer onto said second member through the separation step of separating said second semiconductor layer through said separation layer, and forming a second semiconductor wafer by separating said p-type semiconductor substrate having said first semiconductor layer through said separation layer.
A process for manufacturing a semiconductor wafer according to the present invention comprises the steps of:
forming at least a first semiconductor layer comprising an-epitaxial semiconductor layer having impurity concentration, which defines p-type conductivity, lower than that of a p-type semiconductor substrate; and a second semiconductor layer comprising an epitaxial semiconductor layer having impurity concentration, which defines p-type conductivity, higher than that of said first semiconductor layer; arranged on said p-type semiconductor substrate in the order as mentioned; making said second semiconductor layer and part of said first semiconductor layer porous; and forming a third semiconductor layer onto said second semiconductor layer made porous; thereby forming a first member; and
transferring said third semiconductor layer onto said second member to form a first semiconductor wafer, and forming a second semiconductor wafer comprising said p-type semiconductor substrate having said first semiconductor layer.
A method for using a semiconductor wafer according to present invention is characterized by preparing a seed-wafer which has been used for manufacturing a bonded SOI substrate followed by conducting smoothing treatment on at least one surface of said seed-wafer so as to be sold as a semiconductor wafer without being used for manufacturing the bonded SOI substrate again.